The Notification Oriented Paradigm Language to Digital Hardware as an Intuitive High-level Synthesis Tool

Ricardo Kerschbaumer, André Augusto Kaviatkovski, Gabriel Rodrigues Garcia, Carlos Raimundo Erig Lima, Jean Marcelo Simão

Abstract


The parallelism allowed by FPGAs has attracted attention for knowing applications that need processing power. However, the need for specific and very technical development language has not stimulate its broad use. As an alternative, there are High-level Synthesis Languages (HSL), which allow less complicated FPGA use. However, they do not tend to take full advantage of the FPGA technology. Therefore, another alternative was developed, based on the Notification Oriented Paradigm (NOP), called NOP for Digital Hardware (NOP-DH). NOP allows development in high level with its rule-oriented language called NOPL. Its entity decoupling, parallelism, and redundancy avoidance are useful for best performance. In turn, the NOP-DH brings NOP for the FPGA context with the benefits observed in software but enhanced by hardware nature. This paper reviews the NOPL for NOP-DH (NOPL-DH) that aims high level programming for FPGA. The paper proposes the NOPL-DH test by independent developers, by developing a monitoring device for a box transporting bidirectional conveyer. As a result, NOPL-DH allowed high-level development under the NOP-DH structure in an FPGA, without the need for technical knowledge and, still, maintaining and exploring the NOP properties in FPGA

Keywords


FPGA; Notification Oriented Paradigm (NOP); Notification Oriented Paradigm to Digital Hardware (NOP-DH); NOP Language (NOPL); NOPL-DH; VHDL

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References


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DOI: https://doi.org/10.22456/2175-2745.112006

Copyright (c) 2021 Ricardo Kerschbaumer, André Augusto Kaviatkovski, Gabriel Rodrigues Garcia, Carlos Raimundo Erig Lima, Jean Marcelo Simão

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